Measuring correlation, amplitude probability and probability density distributions, and signal response averaging

ABSTRACT

An online real-time instrument for measurement of auto and cross correlation, amplitude probability distribution and amplitude probability density distributions of random analog signals and for measurement of average signal response characteristics. A scanning averager utilized in all the measurements includes capabilities for adapting its time constant to differing clock rates and for selecting its time constant at will for longer and shorter averaging times and for controlling the range of selfadaptivity. The correlation circuitry includes special timing controls for both basic and high frequency modes and combines analog and digital circuit design. The latter is accompanied by provision of a synchronized pseudo-random noise source to assure uniform probability density distribution for the full scale range of the input signal. Conservation of circuitry is achieved through use of the same circuitry for the different measurements of which the instrument is capable. Special logic is included for enhancement of amplitude probability distribution measurements.

United States Patent [72] Inventor Keith H. Norsworthy OTHER REFERENCESBeIIeVueQWaSh' Gatland et al.: A Correlation Function Computer Using PP,340 Delta Modulation Techniques Inst. of Scient. Instruments [22] FiledJuly 7, 1969 1965 Vol. 2 529 532 Paiemed Dec-7,1971 Princeton AppliedResearch: Signal Correlator Model I Assignee The Boeing p y Correlationfunction computer Nov. I966 Seattle wash Primary Examiner-Malcolm A.Morrison Assistant Examiner-Felix D. Gruber Attorney-Christensen andSanborn [54] MEASURING CORRELATION, AMPLITUDE PROBABILITY ANDPROBABILITY DENSITY ABSTRACT: An online real-time instrument formeasurement DISTRIBUTIONS, AND SIGNAL RESPONSE of auto and crosscorrelanon, amplitude probability distribu- AVERAGING tion and amplitudeprobability density distributions of random 16 Claims 8 Drawing Figsanalog signals and for measurement of average signal responsecharacteristics. A scanning averager utilized in all the mea- [52] US.Cl 235/181, suremems indudes capabilities f adapting its time constant235/150-53' 324/77 324/77 328/29 328/75 to differing clock rates and forselecting its time constant at 328/154 will for longer and shorteraveraging times and for controlling [5 l] Int. Cl ..G06i /34, the rangef selgadaptivity The col-relation circuitry includes 8 7H9 specialtiming controls for both basic and high frequency Field ofSearch235/181, modes and combines analog and digital circuit design The150-52; 324/77 77 G latter is accompanied by provision of a synchronizedpseudorandom noise source to assure uniform probability density dis-[56] References (med tribution for the full scale range of the inputsignal. Conserva- UNITED STATES PATENTS tion of circuitry is achievedthrough use of the same circuitry 3,404,261 10/1968 Lespers et a]235/181 for the different measurements of which the instrument is3,449,553 6/l969 Swan 235/I50.52 capable. Special logic is included forenhancement of am- 3,514,585 5/1970 Norsworthy 235/181 plitudeprobability distribution measurements.

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BACKGROUND AND SUMMARY OF THE INVENTION This invention relates toinstruments for random signal analysis, and more particularly to asingle instrument capable of measuring auto and cross correlationfunctions, amplitude probability distribution (APD), amplitudeprobability density distribution (APDD) and signal response averaging(sometimes referred to as computation of average transients). inaddition, the invention relates to an improved scanning averager,utilized in each of the above-mentioned measurements, capable ofadapting its time constant of different operation speeds (clock rates)and including a feature for selection of the effective time constant tocontrol the averaging time and the selfadaptivity of the averagingcircuits, without changing the circuit values. The invention alsoencompasses certain specific improvements in time correlation computers,particularly in the timing control thereof to effect improved operation.Other features of the invention will become apparent from the disclosureof the preferred embodiment which, it will be recognized, can bemodified in various ways within the scope of the various principlesinvolved.

Over the past decade the evolutionary development of equipment andtechniques for analysis of random signals has steadily decreasedinstrument complexity and improved measurement accuracy to a point whereerrors are now usually attributed to insufficient input data rather thaninstrument imperfections. Various approaches to correlation measurementshave been previously taken, especially in relation to the techniques forobtaining signal delays. These included the use of a magnetic recordingmedium with means for varying the positions of read and write heads.Typically, delay values were processed one at a time, and thecorrelation results were plotted or displayed for interpretation.Multichannel instruments for substantially simultaneous computation ofdifferent correlation coefficients were then developed, as wereinstruments utilizing electronic sample and hold circuitry for derivingthe signal delays required for correlation. Instrument performancecharacteristics were limited, however, by inaccuracies in themultipliers, low-speed sample and hold circuits, and statisticalvariances arising from low product rates.

This inventor developed improved multichannel correlation circuitrywhich, by virtue of a unique cross multiplication of signal valuesappropriately staggered in time, was able to provide on a practicalbasis a larger number of simultaneously computed correlationcoefficients for continuous display of the correlation function in realtime. The design disclosed in the above-mentioned copending applicationpermitted the construction of an economical, compact and easilymaintained system for real time display of the correlation function.

lt became evident, however, that additional efforts were required todecrease the statistical variances that occur from low product rates andto reduce the cost of construction of a multichannel instrument havinglarge amounts of precomputation (bias) delay. It also became evidentthat since correlator applications involve random phenomena, theinstrument could advantageously include additional capabilities forstatistical measurements including amplitude probability statistics, andthat for relatively little cost these capabilities could be added to acorrelation instrument including the appropriate features.

Through evolutionary stages of circuit development the present randomsignal analyzer was developed which provides the features and advantagesmentioned heretofore and also provides the capability of computingaveraged transients or the averaged response of a system to repeatedstimuli.

The greatest disadvantage of prior systems which is overcome by thepresent system is the low product rate characteristic of such priorsystems. The product rate per correlation coefficient in theaforementioned multichannel instrument of the inventor was, for example,1(296 Low product rates produce substantial statistical variance in thedisplay correlation function, particularly when large precomputation(bias) delays are employed. The high product rate provided by thisinvention effects substantial improvements in the quality of thecorrelation measurements achieved while allowing a less costlyimplementation of the precomputation delay than has been possibleheretofore.

in general, the statistical accuracy of a correlator is dependent uponthe product rate applicable to each correlation coefficient outputchannel. If the frequency at which the samples and products are obtainedis too high, then the products averaged in each output channel will behighly correlated, one to the next, so that they do not providestatistically independent data for the averaging process. Of course, ifthe sampling rate is too low, then insufficient signal information isderived for the averaging process.

A product rate (per correlation coefficient) equal to the reciprocal of10 times the delay increment A-r virtually as effective as all higherproduct rates, because the delay increment A1 is typically selectedsmall enough to display the correlation function with acceptable delayresolution. Under this condition products taken with less separationthan IOA'r are not statistically independent and do not contributeindependently to the averaged correlation coefficient.

It should be noted that despite the Nyquist sampling theorem, productrates for each correlator output channel of less than half the inputsignal bandwidth are acceptable. The correct interpretation of thesampling theorem for the correlator is that A-r should be less thanone-half the reciprocal of the input signal bandwidth.

ln addition to achieving a high product rate or correlation coefficientand the other objectives mentioned, the instrument also achieves certainmore specific purposes. For example, by use of both analog and digitalcircuit design and fast circuit components, a delay increment A'r assmall as 0.1 microseconds is provided.

The provision of the pseudorandom noise source whose randomness issynchronized with the instrument cycle enables the use of simple digitalcircuit design without compromising measurement linearity.

In accordance with the invention, the correlation circuitry of theinstrument successively derives samples of first and second signals atdifferent sampling rates and stores sampled values of the signal in amultiple output storage means. During each instrument cycle, each of thestored values of the first signal is multiplied by each of the values ofthe second signal. Hence the Cartesian product of the derived samples offirst and second signals is obtained sequentially by crossmultiplication of the stored values of the one signal by each of thevalues of the second signal. As the products of first and second signalvalues are obtained, they are applied to separate averaging circuits bya scanner which enables the sharing of each of a plurality ofmultipliers among several averaging circuits. The scanner multiplexesthe product signals to the individual averagers so that each receivesonly those corresponding to a given delay value 1'. A suitablenondestructive readout scanner which need not be coordinated orsynchronized with the aforementioned switching circuitry, enables realtime display of the averaged product signal values, which comprise thecorrelation function. In the preferred form of the instrument, digitalsamples of one signal and analog samples of the other signal arederived. Both positive and negative values of the analog samples areprovided, and the multiplication process is achieved by applying to theaveraging circuits positive or negative values of the analog samples inaccordance with whether respective stored digital samples of the othersignals are ones or zeros.

In the basic mode of operation of the correlator the analog samples aretaken at a higher rate than the digital samples to establish anappropriate array of delays 1-. In the high-frequency mode the analogand digital samples are taken at slightly different rates and theiteration caused by the phase difference enables production of a largearray of delays r with small spacings A'r therebetween.

For amplitude probability distribution (APD) measurements much of thesame circuitry is utilized, and means are provided for switching out ofthe system those circuits which are not utilized in this mode and intothe system those circuits which are utilized. The input signal iscompared in a digital comparator (also utilized in the correlatorcircuitry) with a ramp signal which is synchronized with the cycling ofthe scanning averager. Each averaging circuit in the scanning averagerreceives a positive or negative voltage signal, depending upon whetherthe input signal is greater or less than the ramp signal value to whichthat averaging circuit cor responds. Each averaging circuit thus derivesa signal representing the probability of the input signal exceeding aparticular ramp signal value, and their outputs collectively provide theamplitude probability distribution for real time display. A specialenhancement feature is provided by means of which the amplitudeprobability distribution is weighted to improve its representationthroughout the range of ramp signal values.

For measurement of the amplitude probability density distribution (APDD)two digital comparators are utilized, in one of which the input signalis compared with a fixed reference level and in the other of which it iscompared with the ramp signal plus a voltage reference. The comparatoroutputs are coupled to an exclusive OR circuit which provides a signalindicating whether the input signal is greater or less than the fixedreference and less than the sum of the incremental signal and the rampsignal. The digital indication thus derived is applied to the averagingcircuits in synchronism with the ramp signal voltage, whereby theoutputs of the averaging circuits collectively represent the amplitudeprobability density distribution of the input signal.

When the instrument is operated as a signal averager (com puter ofaverage transients) still other special circuitry is switched intooperation while that applicable only for correlation and amplitudeprobability measurements is switched out of the system. In addition tothe input signal representative of the response of a system whosecharacteristics are being measured, an additional input signal isapplied to the instrument for coordination with the stimulus applied tothe measured system. In response to each stimulus trigger, the scanningaverager applies the input signal to the averagers successively wherebyeach averaging circuit averages repeated responses of the measuredsystem for a particular time following applications of the stimulus. Theaveraging circuit outputs collectively provide a representation of theaverage transient response of the measured system.

In the scanning averager each averaging circuit includes a specialsample and hold capacitor which is much smaller than the capacitorincluded in the RC-averaging filter circuit and which enables thescanning averager to automatically adapt its time constant to differingclock rates. If the clock rate, and hence the scanning rate, is highthen the special input capacitor in efiect shields the averaging filterfrom the operation of the input scanning switch so that the filtercircuit does not know that it has been disconnected during a portion ofthe cycle. For lower scanning rates, however, the voltage on the inputcapacitor tends to decay and reach an equilibrium with that in thefilter circuit. For different clock rates, the decay process, or theprogression of the averaging circuit toward an equilibrium state,progresses to different degrees. Since the effective time constant ofeach circuit is dependent upon the amount of time during which it isconnected to the system by the scanner, the input capacitor causes theeffective time constant to adapt to differing degrees for differentclock rates.

In addition, special timing control circuitry is included for selectionof the effective time constant by controlling the dwell time of thescanner input switches. This feature is effective either together withor independent of the adaptivity feature.

These and other features, objects and advantages of the invention willbe more fully understood from the following description of the preferredembodiment of the invention, as illustrated in the accompanying drawingsand diagrams.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram of a randomsignal analyzer according to the invention, including circuitry forselecting different modes of operation for computation of auto and crosscorrelation functions, amplitude probability distribution, amplitudeprobability density distribution, and averaged signal responses.

FIG. 2 is a block diagram of the basic timing circuitry for the analyzerillustrated in FIG. 1.

FIGS. 3 and 4 are timing diagrams for basic and highfrequency modes ofoperation of the analyzer as a correlator.

FIG. 5 is a block diagram of the scanning averager according to theinvention and timing circuitry therefor.

FIG. 6 is a circuit diagram of the preferred form of an in dividualaveraging circuit in the scanning averager.

FIGS. 7 and 8 are diagrams utilized in describing the operation of thescanning averager.

DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred multipurposerandom signal analyzer instrument according to the invention is designedto be contained within a single cabinet with switches on the front panelfor selection of the different modes of operation. The positions ofswitches S to S are shown in table I in the Appendix. The instrument isdesigned primarily as a correlator, with secondary capabilities ofrandom signal analysis by computation of APD, APDD and signal averaging.Correlation analysis will be discussed first, and the switch positionsshown in the drawings are for correlation measurements.

Correlation Measurements For cross correlation first and secondelectrical signals f,(1) and f (t) are applied at first and second inputterminals a and b, with switch S, in position 1 (up). Forautocorrelation the signal is applied at terminal b and switch S isturned to position 2 (down). The specialized case of autocorrelationwill be understood from the following discussion based on crosscorrelation with switch S in position 1.

In the first input channel signal/1(1) is applied through line 10 andswitch 5, in position 2 to a first analog sample and hold circuit 14after being inverted in inverter 18. It is also applied to a secondanalog sample and hold circuit 16 to supply opposite polarity analogsamples to multipliers M,, M M mM on lines 20 and 22. The sample andhold circuits operate under control of a waveform (T, or T,') applied tosample f,(t) at intervals :31 or multiples thereof.

In the second channel signal f,(t) is applied on line 12 to first andsecond digital comparators 24 and 26, whose respective outputs arecoupled to exclusive OR-circuit 28. However, the second digitalcomparator 26 and the exclusive OR-circuit 28 are not used in thecorrelation mode of operation of the instrument, with switch 8,, inposition 2. (Switch 5,, is in position 2 to also exclude the operationof special circuitry leading thereto, described hereinafter, fromoperation in the correlation mode).

Digital comparator 24 compares signal f (t) with either of tworeferences. With switch S in position 2,f,(!) is compared with ground inwhat is termed the relay" mode. With switch S, in position 1, in what istermed the linear" mode,f,(r) is compared with a reference signalprovided by a pseudorandom noise source 30 through switch 5, (inposition 2). It was shown by Jespers, Chu and Fettweis, in A New Methodto Compute Correlation Functions," IRE Transactions on InformationTheory, Vol. IT-8, No. 5, Sept. 1962, pp. 106, I07 and 136, thatcorrelation measurements can be performed,

without sacrificing statistical accuracy, using quantized signals inboth input channels in a so-called zero-crossing" correlator, providedthe quantizing is performed by comparison with auxiliary signals whichhave uniform probability distributions across their full scale range.

Princeton Applied Research Corporation (PAR) has constructed acorrelation function computer utilizing a quantizer which compares theanalog input signal with a sawtooth waveform and samples the output ofthe quantizer at a random rate. In the PAR correlator a very high degreeof isolation must be maintained between the quantizer and the frequencyof the clock which controls the sampling to assure that the sampling israndom. That is, the approach has been to assure that asynchronism ismaintained between the randomness control and the clock frequency, inorder to meet the condition established by Jespers et al. that theauxiliary signals be uncorrelated to the input signals.

The opposite approach is taken in the present correlator, wherein asimpler pseudorandom noise source 34) is purposely synchronized withsampling rate. The random noise source 30 comprises a shift registergenerating a pseudorandom code, of the maximal length sequence type,which by simple binary digital-to-analog conversion gives a uniformprobability distribution over the full scale range of the input signal.Instead of providing circuitry and shielding to assure isolation andasynchronism of the code signal with the cyclic operation of thecorrelator, according to this invention a timing control waveform T (orT from terminal TL is applied at input terminal 32 which, as will beexplained hereafter, cycles the noise source so as to produce thedesired uniform probability distribution over the averaging interval ofthe instrument. The length of the noise source shift register sequenceis such that the sequence is recycled a number of times within eachaveraging time ofthe system.

While the zero-crossing correlator described by Jespers et al. quantizedboth input signals, the present correlator combines digital and analogcircuit design to achieve still greater accuracy on a practical basis.The output of digital comparator 24, namely signal f,,(r) quantized withrespect to either ground or the synchronized pseudorandom noise signal,is applied to a variable bias delay circuit 33 through lines 34 and 36with switches S to S in position 1. Bias delay circuit 38 is a variablelength shift register which enables a selectable amount ofprecomputation (bias) delay to be employed in a known manner to shiftthe correlation function display to nonzero starting points selectablein steps of IOAT up to 5,12OA1' in the preferred instrument. To simplifythe discussion herein, it will be assumed that the bias delay is zero,and that the quantized second input signal f (l) is applied directly toflipflop circuit 40 which is coupled to the output of bias delay circuit38.

In effect, flip-flop 40 samples the output of digital comparator 24under control of a timing wavefonn (T or T from terminal TL, applied toits control terminal 42 through switch 8,. The quantized samples thusderived are applied through switch S, and line 44 to a distributionshift register 46 having Q stages and parallel output terminals 48. Theregister is shifted under control ofa timing waveform (T or T applied atcontrol terminal 50. The quantized samples of f,(!) as they are shiftedthrough successive stages of the shift register 46 are distributed inparallel to multipliers M1,, M M ...M through OR-circuits 52. A groundreference voltage or zero is applied to the other input of each ORcircuit through switch S, in position 2.

Multipliers M,...M are one-bit multipliers which provide at theirrespective output terminals 54, 56, 58...) positive or negative analogsamples of the first input signal f,(l) in accordance with whether theapplied quantized sample of (1) is a one or a zero. These productsignals are applied to the respective inputs of the scanning averager62.

Scanning averager 62 operates under control of a timing waveform (T, orT,') from terminal TL, applied to control termind] 64, whichsynchronizes the scanner operation with the sampling of the inputsignals as will be described. In the correlation mode the productsignals from the respective multipliers are applied in parallel to Qsets of averagers, each set consisting of P separate averaging circuits:A,,, A,,...A, A A ,...A Qll, A UA These separate sets of averagingcircuits are scanned in parallel in the correlation mode so that inputscanners SC,, SC,, SC ...SC apply respective product signals to thefirst averaging circuit in the corresponding sets simultaneously, thento the second averaging circuit, then to the third, and so forth. Thereadout scanner 66 operates independently of the input scanners andprovides nondestructive readout of the averaged product signals in therespective averaging circuits for real time display on an oscilloscopeor other suitable instrument coupled to the display output 68.

Hereafter the discussion proceeds on the assumption that P=l0 and Q=3.FIG. 2 shows the basic timing control circuit for operation of theinstrument in its several modes. A 10 megacycle clock circuit 70 appliesa suitable square wave pulse train to a variable frequency divider 72.The pulse train 74 thus provided is applied to a master control ringcounter 76 which has a capability of being switched between 10- tenandll-stage operation for basic and high frequency correlator modes,respectively. In the basic correlator mode, mode switches 5, S and S arein position 2. A timing waveform having a frequency of one-tenth of thebasic pulse train 74 is generated at the first terminal K, of ringcounter 76 and is applied through mode switch S to a second lO-stagering counter 78. This waveform (T,), provided at terminal TL, and shownin FIG. 3, is used for control of sampling off,(l). In the basiccorrelator mode the pulse interval A1 is equal to IOAI, where A! is thedivided clock interval, i.e., the period of waveform 74 (FIG. 2).

The waveform at T, is also applied to one terminal of an optionalAND-circuit 80, to the other terminal of which is applied the waveformappearing at the first output terminal J, of ring counter 78. This ANDcircuit is preferably included in order to obtain a sharp, preciselytimed pulse for every tenth T, pulse. The pulse train (T thus createdhaving an interval IOAT (see FIG, 3) as provided at terminal TL throughswitch S is used for controlling sampling of quantized signalf,(t) byflip-flop 40 (FIG. I).

A third timing waveform is provided at terminal TL Flipflop 82 has asits set input the divided clock pulse train 74 and as its reset inputthe output of AND-circuit 80 (waveform T Thus flip-flop 82 is set at alltimes except when a reset pulse is provided every lOA-r by the waveformT,. It provides an output pulse when reset, so that the waveform createdis delayed by 0.5At with respect to the T waveform, as shown in FIG. 3.It should be noted that each timing waveform pulse in the basiccorrelator mode has a width equal to A'r/ 10, and T, pulses follow Tpulses by Ar/ZO or 0.5At.

Therefore, in the basic correlation mode, analog sample and holdcircuits l4 and 16 (FIG. 1) are operated under control of waveform T, tosample the inverted and uninverted form of analog input signal f,(t) atintervals Ar. Flip-flop 40 is operated under control of waveform T tosample quantized input signal f,(r) at intervals lOAr, and each suchsample is shifted into and through the distribution shift register 46under control of delayed waveform T of the same frequency.

Hence multiplier M,, for example, receives a new sample of f (t) eachlOAr, and multiplies that signal value by the next succeeding 10 samplesof f,(t) provided at terminals 20 and 22. The same f (t) sample is thenshifted to stage 2 of the distribution shift register and is multipliedby the next succeeding samples off,(t), while a new sample shifted intostage 1 of the shift register is multiplied by the same succeeding 10samples of f,( r), and so forth. Each sample of f (t) stored in thestages of register 46 is multiplied in the respective multipliersresponsive thereto, by the identical l0 f,(t) samples successivelyderived in the analog channel.

During each interval lOAr, 10 products are obtained by each multiplier,each corresponding to a different time delay (multiple of A1). These aremultiplexed to the separate averaging circuits under control of waveformT,, so that each averager receives a product signal at each intervalIOA-r. Thus A1 is the product interval per correlation coefficientoutput.

Table II shows the resulting delay sequences for the first threemultiplication channels. Each row opposite the designation M,, M,, andM, indicates the delays in units of A1, while immediately below thedelay indication is a designation of the time when the samples of f,(!)and f,(t) respectively, were taken, also in units of Ar on either sideof time zero. The minus signs indicate samples taken before the timeselected as zero for reference purposes. Thus it is seen that in anyinterval lOA-r (time zero through time nine) 30 product signals areobtained, corresponding to 30 different corresponding time delays.

Specific circuitry for controlling the multiplexing of the productsignals to corresponding averaging circuits in the scanning averager 62is illustrated in F IG. 5. The basic divided clock waveform T, atterminal 64 is applied to a P-stage ring counter 86 through switch 8,,in position 1. The X outputs of ring counter 86 are applied throughfield-effect transistor (FET) drivers 88 to the X control terminals ofthe averagers. In the matrix shown all of the X, terminals in the firstcolumn of averagers A,,, A,,...A are energized simultaneously, then theX, terminals, etc.

The last output of ring counter 86 steps a Q-stage ring counter 90 whoseY outputs control the Y terminals of the averaging circuits through FETdrivers 92 and inhibit circuitry 94 discussed hereinafter. In thecorrelation mode A switch 8,, (in position 2) applies to a terminalcommon to all of the FET drivers 92 a signal which causes all of the Yterminals to be energized simultaneously in the absence of the inhibitoverride control 94. Hence for correlation the separate sets ofaveragers respectively coupled to the multiplier terminals 54, 56,...60are operated in parallel, stepped simultaneously by the X outputs of theP-stage ring counter.

As indicated previously the readout scanner 66 is operated independentlyof the input scanners in the scanning averager. An oscillator 96 steps aP-stage ring counter 98 to successively energize output terminals A,, AmA through FET drivers 100, and the last stage thereof steps a Q-stagering counter 102 to energize output terminals 8,, B,...B through FETdrivers 104, the latter being stepped one step for each cycle of P-stagering counter 98 to read all of the averaging circuits in the matrixsequentially. Thus, the separate averaged signal values are applied insuccession to display terminal 68.

When the instrument is operated as a correlator in the high frequencymode, switches S,,,, S and S, are placed in position 1, and ring counter76 is switched to its high frequency 11 stage) mode whereby the laststage thereof is utilized. The circuitry shown in FIG. 2 then providesthe timing waveforms T,', T, and T shown in FIG. 4. The divided clockwaveform is applied as before to the input of ring counter 76, and alsoto the 10-stage ring counter 78. Since counter 76 has one more stagethan counter 78, iteration occurs so that the two counters are in phaseonly once in every 10 cycles ofcounter 76.

The first terminal K, of the 1 l-stage ring counter 76 again providesthe basic control waveform T,', emitting a pulse on every eleventh cycleof the divided clock waveform. In FIG. 4 the pulses are numberedcorresponding to the cycles of the di vided clock waveform starting fromany given time zero. The second control Waveform T,, which controlsflip-flop 40, is obtained from the first output terminal J, of IO-stagering counter 78. The pulses of this waveform are separated by 10 basictime units Ar. Thus 1 1T, pulses occur for each 10 T, pulses andcoincidence occurs every 1 10 cycles of the divided clock waveform.

It would appear at this point that one sample will be lost and notmultiplied in view of the iteration. However, this is not the case,since a special timing control is provided to efiect an extra shift inthe distribution shift register 46 for each 10 cycles of ring counter 76and thereby achieve a multiplication of all samples obtained, whileobtaining the same array of Q- delay times.

To provide the extra shift pulse an AND-circuit 106 is coupled to thelast outputs K,, and J,,, of ring counters 76 and 78, respectively, toprovide a coincidence pulse which occurs just prior to each 1 10th cycleof the divided clock waveform, just when the two counters are about tocycle once in phase. The coincidence pulse is supplied at tenninal TL,through circuit 108 and switch S, at time 109. Except for the extrapulse the T, waveform is identical to the T, waveform but delayedtherefrom by 0.5At because of the interposed flip-flop I10.

Comparing waveforms T, and T, in FIG. 4 it is seen that flip-flop 40samples f,(t) once each 10th time unit, and each sample is shifted intothe shift register 46 by T," pulses which occur after a delay whichincreases by one time unit per sample, until the digital sample taken attime is shifted into the register at time 99.5. As the digital samplestaken at times 0, I0, 20 etc., are shifted into the register they aremultiplied by analog samples taken at times 0, l l, 22, etc. The firstset of ar rows in FIG. 4 indicate the pairing of digital and analogsamples, while the second set of arrows indicate the shift of digitalsamples. The digital sample taken at time 90 and shifted into the firststage of the register at time 99.5 is multiplied in multiplier M, by theanalog sample taken at time 99 (1'=9A'r).

If the extra pulse were not provided, the digital sample taken by theflip-flop 40 at time 1 10 would cause the loss of the sample taken attime 100 before it could be shifted to the shift register, which shiftwould normally not occur until time 100.5. The statistical sampling ofthe signal f,(!) and the correlation measurement would be therebydistorted.

The extra pulse thus shifts the digital sample taken at time 100 intothe first stage of the shift register at time 109. This sample isimmediately shifted again at time 110.5 when the digital sample taken attime 1 10 is shifted into the first stage of the register. Therefore,the digital sample taken at time 100 is not multiplied in multiplier M,,but only in multipliers M,, M etc., and this is true of each 1 1th or(P-H )th digital sample. Each such sample is shifted through the firststage of the dis-- tribution register between the time the scanner makescontact with two adjacent averaging circuits.

The time delay sequences thus established for the high frequency modecan be verified by reference to table II] wherein the delays 1 are givenin units of Ar in rows opposite the multiplier designations M,, M, and MImmediately below the delays the timing of analog and digital samplesare given, just as in table II for the basic correlation mode. Note thatno digital sample taken at time 100 appears in the M, row.

It will be observed that the product interval for each correlationcoefficient output in the high frequency mode is l lOA'r, since in onescan of the input scanners SC,, SC,... each averager receives one of the10 products obtained during that scan, and the products are separated byintervals 1 Mr, that is (P-l-l )A-r. See FIG. 4. In contrast, the peroutput channel product interval in the basic mode is IOAT, productsbeing obtained every interval A-r. See FIG. 3. However, the delayincrement is smaller. For the higher frequency mode Ar=Al (the clockinterval), whereas for the basic mode AFIOAI. Thus higher resolution(better definition) is obtained in the high frequency mode by smallerseparations of the correlation coefiicient, though at a slight sacrificein statistical accuracy because of the lower product rate percoefi'icient.

However, it has not been possible heretofore to obtain A-r as small asin the high frequency mode of this instrument. When possible, the basiccorrelator mode should be used if a particular required delay incrementcan be obtained thereby, in preference to using the high frequency mode,since the basic mode provides better statistical accuracy. However, whenthe required sampling or delay interval A1- is too small for the basicmode, then the high frequency mode will give good statistical accuracy.As indicated previously, the reduction in statistical accuracy isnegligible, since products obtained at a higher rate would not providestatistically independent data.

9 Amplitude Probability Distribution When the random signal analyzeraccording to the invention is operated to compute the APD of a signal,much of the same circuitry heretofore described with reference to thecorrelation mode of operation is utilized. The signal whose APD is to berandom is applied as signal f,(t) to terminal b. Switch S, may be ineither position, since ganged switches S to S, are in position 1. Thesignal is applied through line 12 to first and second digitalcomparators 24 and 26 whose outputs are connected to exclusiveOR-circuit 28. However, digital comparator 26 and exclusive OR-circuit28 are not utilized in this mode (just as in the correlator mode), sinceswitch S is in position 2. Switch 8,, is in position 1 for this mode, sothat the circuitry leading thereto is utilized, as will be describedhereinafter. v

The digital comparator 24 compares the input signal with a ramp signalgenerated by a suitable digital ramp generator 112 and supplied to thecomparator through switch 8, in position 2 and, S,,, in position 1. Thusat any instant the digital comparator provides a quantized outputrepresenting the probability of the input signal being greater or lessthan the ramp function provided generator 112. The quantized output 34is supplied through switch 8-, in position I to variable bias delaycircuit 38 and flip-flop 40. However, to assure that this circuitry isnot utilized in the APD measurement flip-flop 40 is held in its resetposition by an auxiliary reset terminal I14 connected to ground throughswitch S in position 1, thus providing only zeros to the shift registerinput 44 and hence to OR-circuits 52.

The quantized output of comparator 24 is applied through switch S, inposition 2 and switch S, in position I to line 116 and OR-circuits 52,and hence to multipliers M,, M,,...M

In the analog input channel switch S in position I connects the sampleand hold circuits to a reference voltage V,, so that positive andnegative reference levels are applied to the multiplier circuits throughlines 20 and 22. All of the multipliers receivethe same quantizedprobability signal through common input 116 to OR-circuits 52, and thissignal appears as :V, at each of the multiplier outputs 54,56, 58...60.

However, the probability signal is applied to the averagers in thescanning averager 62 only one at a time (not in parallel as in thecorrelation-mode), by virtue of an altered form of operation thereof.Referring to FIG. 5, switch 8,, coupled to FET drivers 92 is in position1 for the APD mode, so that the Y-output terminals of Q-stage ringcounter 90 are energized one at a time as they are stepped byenergization of the last output X}. of the P-stage ring counter 86.Hence the averaging circuits A A, ...A, in the first set are connectedsequentially to multiplier M,, then the second set of averagers A A mAare connected to multiplier M and so on until the final set of averagingcircuits A A WA are connected sequentially to multiplier M Both the rampfunction provided by generator 112 (FIG. I) and the scanner arecontrolled by the same timing waveform T, so that they are recycledtogether. The stairstep-type ramp function steps to a new value for eachstep of the scanning averager 62. It is recycled by pulses at inputterminal 119 thereof, derived through an AND-circuit I20 (FIG. 5) bycoincidence of counter outputs X and Y,,, which occurs at the end ofeach complete cycle of Q-stage ring counter 90.

The probability signals resulting from comparison of the input signaldiscrete values of the ramp function are thus multiplexed to theappropriate averagers, each of which provides a signal averagerepresentative of the probability of the input signal being greater orless than the particular value of the ramp function to which iscorresponds. The outputs of the averaging circuits collectivelyrepresent the amplitude probability distribution for the input signal,which is displayed in real time by independent operation of the readoutscanner 66 and suitable display means coupled to output terminal 68.

The ramp function is typically chosen to rise from a negative value to apositive value, with the lowest (starting) value being chosen so thatthe probability of the input signal being less than the ramp function atits lowest values is small. In order to enhance the APD outputrepresentation, special enhancement logic is provided including a binarycounter circuit (FIG. I) stepped by the signal provided at terminal T,(FIG. 5). Counter 120 preferably comprises a three-bit binary counterhaving three parallel outputs to a NAND-circuit 122. The NAND circuit ischosen in order to provide a weighing function having a ratio of 7 to 8.That is, it provides an output for seven out of every eight cycles ofthe scanning averager. Special inhibit circuit 124 coupled to the outputof NAND-circuit 122 inhibits the input gates to the averaging circuitsfor seven-eighths of the time, except when digital comparator 24produces a one indicating that the input signal is greater than the rampfunction.

The modulated inhibit signal from comparator 24 and inhibit circuit 124is applied at terminal TL, through switch 8,, in position 1 to one inputof an OR-circuit (FIG. 5), which controls the inhibit circuits 94interposed between the Q-stage ring counter 90 and its FET drivers 92.With an inhibit instruction from NAND-circuit 122 neither a positive nornegative reference signal value V,, is applied to the averager. Theenhancement logic thus imposes a seven-eighths weighing function on allzeros supplied by digital comparator 24, without affecting theapplication of ones of the averaging circuits. This introduces somenonlinearity into the APD function (and to the APDD function describedhereinafter as well). However the nonlinearity is acceptable in view ofthe enhanced APD measurement for low ramp function values.

Amplitude Probability Density Distribution The APDD mode of operation isvery similar to that for APD, and all switch positions are the sameexcept switch 5,, which for APDD is in position 1. The ramp functionoutput of generator 112 supplied through switch S is added inADD-circuit 132 to a small voltage increment AV, supplied by a suitableDC voltage source 134, and the sum is applied to digital comparator 26.

While digital comparator 24 compares the input signal f,(!) directlywith the ramp function, digital comparator 26 compares it with the rampfunction plus AV,. Comparator 24 measures the probability of the inputsignal being greater than the ramp function, while digital comparator 26measures the probability of the input signal being less than the rampfunction plus AV,. Comparator 24 applies to exclusive OR-circuit 28 azero if f,(t) is greater than the ramp voltage at a given instant and aone if it is less than the ramp voltage. Comparator 26 applies toexclusive OR-circuit 28 a zero if f,(!) is greater than the ramp voltageplus AV and a one if it is less than that sum. Exclusive OR-circuit 28applies a zero to switch S, if both its inputs are zero or if both areone, thus providing a zero when the input signal is either smaller thanthe ramp voltage or greater than the ramp voltage plus AV,. A one issupplied to switch S, only in the even that the input voltage at a giveninstant is greater than the ramp voltage and less than the ramp voltageplus AV, and hence is within AV, of the ramp voltage. (The condition off,( I) being less than the ramp voltage but greater than the rampvoltage plus AV, never occurs).

Since the ramp function provided be generator 112 is synchronized withthe scanning averager 62, which scans all of the averagers in sequencecorresponding to the advance of the ramp function through its sequenceof values, each averaging circuit computes the probability of the inputsignal being within AV, of the ramp voltage value to which itcorresponds. The averaging circuits collectively provide in real timethe APDD function accordingly. This function is modified, however, bythe enhancement logic described heretofore in connection with the APDmode of operation.

Signal Averaging When the instrument is operated in the signal-averagingmode, sometimes referred to as computation of average transients, thepurpose is to measure the average response of a system to a repeatedstimulus. For example, an electronic system whose response to a givenunit voltage input is to be measured, is subjected to a repeatingstimulus and its output signal is applied as the input to the presentinstrument. In addition, the stimulus, or a suitable trigger voltagesynchronized with it, is applied to input c, which is one input to adigital comparator 136 serving as a level detector. The other input tocomparator 136 is a reference V, derived from a suitable DC source 138.Comparator 136 thus supplies an input to flip-flop 140 when the stimulusvoltage applied at terminal c exceeds the reference voltage V,,.

Timing waveform T, is applied to the reset terminal of flipflop 140, sothat immediately following reception of the stimulus voltage flip-flop140 applies an input to one terminal of an AND-circuit 142 and to thereset terminal of flip-flop 144. However, flip-flop 144 will not providean output to the other terminal of AND-circuit 142 unless it has beenset by a signal at terminal TL which referring to FIG. 5, occurs at theend of each cycle of the scanning averager with coincidence of signalsat terminals X, and Y Flip-flops 140 and 144 and AND-circuit 142 thuscomprise lockout logic causing the instrument to ignore any stimulussignal arriving at terminal 0 following a given stimulus by less thanthe time required for the scanning averager to complete one scan.

With switches to S in position 2, the output of AND-circuit 142 isapplied to variable bias delay circuit 38. This circuit provides thecapability of interposing a delay between arrival of the stimulustrigger at input c and the beginning of the scan of scanning averager62. Following the delay thus selected. if any, the start signal issupplied to the set terminal of flip-flop 40 whose output signal issupplied through switch S, to terminal TL Terminal TL, is the setterminal of a flipflop 146 (FIG. 5), the reset terminal of which isconnected to terminal TL, which supplies the indication that thescanning averager has completed its scan. The output of flip-flop 146 isthus applied to an AND-circuit 148 only in the event that the scanningaverager has completed its scan and after the interposed period of biasdelay has elapsed. AND-circuit 148 permits waveform T, to step ringcounter 86, through switch 8,, in position 2. Since switch 8,, is inposition 1 the scanning averager scans all of the averaging circuitssequentially before returning to its start position. Following acomplete scan of the scanning averager flip-flop 144 (FIG. 1) conditionsthe instrument to accept the next stimulus trigger voltage at terminalc, as previously described.

The signal representing the output of the system whose response is beingmeasured is preferably applied at terminal a as signal f,(!), withswitch S, in position 1. With switch S, in position 2, sample and holdcircuits 14 and 16 provide positive and negative representations of theresponse signal on lines 20 and 22 to each of the multiplier circuitsM,, M,, M;,...M,,. Since switch 5, is in position 2 the OR-circuits 52provide zeros to the multipliers and shift register 46 is out of actionwith switches S, to S, in position 2. Thus only one side of eachmultiplier is used, thereby transmitting the analog samples of the inputsignal to the averaging circuits under control of timing waveform T,applied to the sample and hold circuitry. Since the stepping of thescanning averager is coordinated with the analog sampling of the inputsignal by waveform T,, the analog samples of the response signal aresuccessively applied to the averagers at times successively delayed fromarrival of the stimulus voltage at terminal 0. After successiveapplications of the stimulus over a period equal to the time constant ofthe scanning averager, each averaging circuit provides a signalrepresentative of the average response of the measured system for thedelay time to which each such averaging circuit corresponds.

The readout scanner 66 supplies at output terminal 68 a representationof the entire average response function of the system, displayed in realtime so that the response of the measured system can be observed whilethat system is adjusted or the stimulus applied to it is altered.

Effective Time Constant Of The Scanning Averager In accordance with thepreferred form of the invention each of the averager circuits in thescanning averager has the basic structure shown in FIG. 6. Each includesinput and output switches S, and S which correspond to individualFET-gates controlled by AND-circuits to which X and Y or A and B inputsare applied as indicated in FIG. 5. Product signals from a multiplierare applied at input 1', while output terminal 0 corresponds to displayoutput terminal 68. Resistance R and capacitor c, are the basicaveraging circuit, while capacitor C, is a sample and hold capacitor ofmuch smaller value than capacitor C conferring upon the circuit uniqueoperational features in combination with the timing control features ofthe instrument.

Each averaging circuit operates intermittently, of course, withoperation of the input scanner. A product signal is available to aparticular averaging circuit during only a portion of the instrumentcycle. In the basic correlation mode this portion is equal to afraction! (FIG. 7) of the delay (sampling) increment of time A-r, whileduring the remainder of the cycle (greater than (P-I )A-r) productsignals are being applied to other averaging circuits.

During the intervening period between closures of switch S, the productsignal last received and sampled by the sample and hold capacitor C,tends to decay toward the voltage V on capacitor C, as indicated in part(A) of FIG. 7. That is, the two capacitors tend to approach equilibriumbetween applications ofa product signal, in accordance with a compositedistribution (or series) time constant RC of the averaging circuitincluding capacitor C,. Since C is much smaller than C,, this timeconstant is very nearly equal to RC,.

With reference to part (A) of FIG. 7 it can be seen that the decay rateduring this off period is always of the same form, being dependent onlyon capacitor and resistance values. If the clock rate is increased(smaller product interval), the approach toward equilibrium in theaveraging circuit will progress to a lesser extent than for a lowerclock rate (larger product interval). This is illustrated by the dottedpulse 150, indicating the lessened availability or dwell time, anddotted line pulse 152, indicating the smaller interval between dwelltimes. The dotted line decay function 153 shows that the voltage oncapacitor C, will tend to approach a value C,,' which is greater than Vthat is, less decay has taken place.

In the absence of capacitor C, the input voltage would immediatelyassume the voltage V when switch S, is opened. With capacitor C, in thecircuit, product rates within a predetermined range determined by itsvalue will result in a residue of charge or voltage remaining oncapacitor C, when a new product signal is applied, because a fraction ofthe previous product signal is still held on the capacitor. The higherthe product rate is, the larger this fraction will be, on the average.

This affects the averaging time constant of the circuit in such a waythat for higher product rates (smaller product intervals) the effectivetime constant is less, and and for lower product rates it is greater.The advantages flowing from this automatic adjustment are very apparent,since a shorter averaging time constant is needed for higher productrates, and vice versa, but it would be quite impractical to changecircuit components to make the adjustment.

Another representation of the adaptivity feature is shown in part (A) ofFIG. 8, which is a plot of the effective time constant T, versus thedelay increment of sampling interval Ar. Each curve represents theeffective time constant T, for sampling intervals A'r up to a samplinginterval which is large compared to the distribution time constant RCeffective in the redistribution of charge when S, is open. With A-r RCthe product samples are held on C, without significant decay betweensuccessive closures of switch S, and the effective averaging timeconstant T, is then approximately equal to RC,. For very high-productrates, therefore, C, has the effect of hiding" the fact that S, is openfor most of the instrument cycle.

When A-r RC the product samples temporarily stored on C decay completelyto the voltage on C during the initial time following the opening ofswitch 5,. The effective averaging time constant T, then approximatelyequals RC, muling circuits without altering the values of the componentstherein and for automatic adaptation of the time components therein andfor automatic adaptation of the time constant to different instrumentoperation rates. The scanning averager is tiplied by a factor closelyrelated to the duty factor of the therefore particularly suited toconfer upon the random signal switch S, analyzer provided by thisinvention a flexibility not heretofore When A1 is comparable with thedistribution time constant possible. Such flexibility is particularlyimportant when the in- RC, an intermediate value ofeffective averagingtime constant strument is operated as a correlator suitable for bothnormal is obtained according to the curves shown in H6. 8, from and highfrequency modes of operation, and when it is which it is apparent thatthe effective time constant T, auto operated as a signal averager(computer of averager matically adjusts itself according to the value of131 selected, transients) this flexibility permits wide selection of thewithin a predetermined range of values of Ar. response measurementperiod and sampling interval A1.

The effective time constant of the scanning averager can also bealtered, again without changing circuit components, by altering thepercentage of dwell time of the scanner switches Conclusion S.Refe' tFl.i 0 G a inanual .dwen time seiecpvny The random signal analyzerdisclosed herein is particularly switch 154 15 included to permitselection of any of the intersuited for low-cost random signal analysison an online, real mediate output terminals K: to Kg of the 10- or Il-stage ring 4 time basis. enabling measurements of correlation. APD,counter 76. The output of the switch 154 is applied to the set 2O APDD,and signal averaging in a single compact instrument. terminal of aflipflop 156, whose reset terminal is coupled to I {h d t t t l K f t 76A t in addition, a unique scanning averager adapted for use in s a 2 a g2 g such measurements (and others) is provided. Modifications g f g f gz 9 P g a g and adaptations of the disclosed system or any of its e f anT 2: E i 94 g subsystems within the scope ofthe basic principlesinvolved as w use ou pu ls app o e n circuitry Intel-pose defined in theappended claims will be recognized by those between the outputs ofQ-stage ring counter 90 and the FET Skilled in he an drivers 92. Theinhibit circuitry 94 responds to the TL lowi 3.23mi: lne.iii?lnifililfl3:21:31; 2:31: y g p TABLE I.SWITCH POSITIONS 1 energization of the nextcounter output, such as K,, to which the selectivity switch I54 isconnected. The Y output to the Correlation averager input switches thusdetermines the dwell time of the Auto Cross Relay Linear APD APDDAvergga input switch whether switch S is in the allow all" or in the s uallow one at a time position. w 2 1 Part (B) of FIG. 8 shows that if thedwell time d were 2 2 2 l 2 selected as equal to the interval Ar, thenthe effective time i i 1 1 2 constant T, would be equal to the timeconstant multiplied by g Q i i P, where P is the number of averagingcircuits with which each 2 2 1 1 2 multiplier is shared. If 10 averagingcircuits are included in 1 1 l 1 2 each set (P=l 0), then the effectivetime constant T, for d=Ar 1 Absence of number means either position ispermitted.

TABLE II.-DELAY SEQUENCES IN BASIC CORRELAIOR MODE Time interval (unitsof A-r) 0 l 2 3 4 5 6 7 8 9 10 11 Sample delays (units of Ar)Multiplers:

M11'- 0 1 2 3 4 5 6 7 8 9 0 1 [,(t) f (t) 0 0 01 0 2 0 3 O 4 0 5 0 6 0 70 8 0 9 10 10 10 11 Mar- 10 11 12 13 14 15 16 17 l8 l9 l0 l1 f ([)f(t;)-v -10 0 -10 1 -i0 2 -10 a -10 4 -10 5 -10 6 -i0 1 -10 s -10 9 -0 100 ii 31- 20 21 22 23 24 25 26 27 28 29 20 21 j;(t)f;(t) -20 0 -20 1 -202 20 3 20 4 20 5 -20 6 -20 7 -20 8 -20 9 -10 to -10 11 TABLE III.DELAYSEQUENCES IN HIGH FREQUENCY MODE Time interval (units of Ar) 0 11 22 3344 55 66 77 88 99 11 121 132 Multiplier: Sample delays (units of A1) 1-r- 0 2 3 4 5 6 7 J 0 1 fz( )fi( 0 0 10 1t 20 2: .io 33 40 44 so (is '1730 as no 99 110 110 120 121 130 132 12 13 14 15 i6 17 18 19 10 11 i2 i022 20 33 30 44 40 55 50 66 0 77 70 88 00 110 121 132 22 23 24 25 26 2728 2E) 20 21 Z2 0 22 10 33 20 44 30 55 40 66 50 77 b0 88 70 99 )0 110100 121 110 132 is l0 RC. For d=A1'/2, T ZO RC, and for d=A1/4, T,,f40What is claimed is: RC. 1. A system for analysis of first and secondelectrical signals,

FIG. 8 also shows that the different selected dwell times comprising:result in different effective times constants with somewhat difa. firstsampling means for providing samples of the first ferent adaptivitycapabilities, as approximately defined by the 70 signal; curves shown.b. second sampling means for providing quantized digital Hence thecombination of the special RC averaging circuit samples ofthe secondsignal; including sample and hold capacitor C,, with the frequency 0. ashift register coupled to the second sampling means for and dwell timecontrols 51 (FIG. 6), provides a unique capareceiving and storingsuccessively derived values of said bility for extending the effectivetime constant of the averag- 75 quantized digital samples, said registerhaving Q-stages into which said samples are shifted sequentially, whereQ is an integer;

d. multiplying means having Q multiplication channels, each channelbeing coupled to the first sampling means and to one of the shiftregister stages for multiplying said quantized digital samples storedtherein by samples from said first sampling means;

e. averaging means including Q sets of separate signal averagers, eachset being response to one of said multiplication channels, respectively,and each consisting of a plurality P of said averagers, where theproduct P(Q) equals the number of desired output values;

f. scanning means for intennittently connecting each of said Omultiplication channels successively to each of the P averagers in theset of averagers responsive thereto; and

g. timing control apparatus including:

i. first control means coupled to the first sampling means to effectsampling of the first signal at intervals NAT, where N is an integerequal to unity, P+l or P-l;

2. second control means coupled to second sampling means to effectsampling of the second signal at inter vals MA-r, where M is an integerequal to P;

3. third control means coupled to the shift register to effect shiftingof second signal samples at intervals RA-r, where R is an integer equalto one of the integers N and M, and

4. fourth control means coupled to the scanning means for effectingconnections of each multiplication channel to the separate averagers inthe set responsive thereto, sequentially at intervals NAT.

2. The system defined in claim 1 wherein:

a. said timing control apparatus includes mode selection meansestablishing a first mode of operation, including:

1. first means altering said first control means to effect sampling ofthe first signal at intervals A1-(N=l and 2. second means altering saidthird control means to effect shifting of said shift register atintervals MA1( R= M); and

b. each of said 0 sets of averagers includes plurality M of saidaveragers (P=M).

3. The system defined in claim 2 wherein:

a. said mode selection means establishes a second mode of operation insaid system:

i. wherein said first means alters said first control means to effectsampling of the first signal at intervals NAT, where N l;

2. further comprising third means altering said second control means toefi'ect sampling of the second signal at intervals (Nl)A-r or (N+l )AT,whereby M=Nl or N-H;

3. said second means alters said third control means to effect shiftingof said shift register at intervals NAT, whereby R=N; and

b. said third control means further includes an auxiliary control forshifting said register one extra shift for each Nth shift thereof.

4. The system defined in claim 3 wherein said timing control apparatusincludes:

a. variable frequency clock means for providing a basic timing waveform;

b. said first control means and said fourth control means include a ringcounter having M+l output stages successively energized in response tosaid basic timing waveform;

. said first altering means of said mode selection means utilizes said Moutput stages thereof for said first mode of operation and utilizingsaid M+l output stages for said second mode of operation;

d. said first control means and said fourth control means each includingmeans coupled to the first output stage of said ring counter.

S. The system defined in claim 4 wherein said timing control apparatusfurther includes:

a. a second ring counter within said second and third control meanshaving M output stages successively energized in response to an appliedtiming waveform;

. said third altering means of said mode selection means furtherincluding a switch coupled to the first output stage of the firstmentioned ring counter and to said clock means for selectively applyingto the input of said second counter the waveform provided at the firstoutput stage of said first mentioned ring counter for first mode ofoperation and applying said basic timing waveform thereto for saidsecond mode of operation; and

c. said second and third control means include means coupled to thewaveform provided at the first output stage of said second ring counter.

6. The system defined in claim 1 wherein said timing control apparatusincludes:

a. first means altering said second control means to effect sampling ofthe second signal at intervals (Nl )A1- or (N+l )AD'r, whereby M=Nl orN+l and N l;

b. second means altering said third control means to effect shifting ofsaid shift register at intervals NA-r, whereby R+N;

. said third control means further includes an auxiliary control forshifting said register one extra shift for each Nth shift thereof; and,

d. each of said O sets of averagers includes a plurality N-l or N+lofsaid averagers, whereby P=Nl or N-l-l. 7. The analyzer defined inclaim I wherein said second sampling means includes:

a. a digital comparator for providing said quantized digital samples ofthe second signal with respect to a reference signal,

b. reference signal generating means for generating a psuedoransomdigital code having a uniform probability distribution over the fullscale range of the second signal to be applied to said analyzer, saidgenerating means being responsive to said second control means forstepping from one value of said code to the next in synchronism withsampling of said second signal, and

c. means for connecting said generating means to said comparator.

8. The analyzer defined in claim 1, including:

a. a digital comparator for providing said quantized digital samples ofsaid second signal with respect to reference level,

b. a variable length shift register interposed between said comparatorand the first-mentioned shift register for providing a selectable amountof precomputation delay prior to multiplication of said first and secondsignal samples, and

c. means coupling said variable length shift register to said secondcontrol means for shifting said quantized digital samples of said secondsignal at intervals MAT.

The analyzer defined in claim 1, further including:

a. means for generating a ramp signal,

b. means for comparing the second signal with said ramp signal andproviding said quantized digital samples indicating whether the secondsignal is greater or less than said ramp signal,

. means for rendering said shift register ineffective and for applyingsignals corresponding to said quantized digital samples to saidmultiplication means output channels,

. fifth control means coupled to the scanning means to effectintermittent connections of said separate averagers to said outputchannels in sequence whereby the averagers in the first set areconnected sequentially, followed by those in the next set sequentially,through all sets, and

e. sixth control means coupled to said ramp signal generating means toeffect one repetition of said ramp signal in synchronism with eachcomplete sequence of connections by said scanning means.

10. The analyzer defined in claim 9, further including:

a means for providing a constant-level reference signal AV and adding itto said ramp signal to form a sum signal;

b. second comparing means for comparing said second signal to said sumsignal and providing quantized signal values indicating whether thesecond signal is greater or less than said sum signal;

c. an OR circuit responsive to both of said comparing means forproviding said quantized digital samples indicating whether said secondsignal is within AV of said ramp signal; and

d. means for preventing application of said quantized digital samplesfrom the first comparing means to said multiplication means outputchannels and applying thereto said quantized digital samples provided bysaid Or circuit.

11. The analyzer defined in claim 9 further including weighting meanscoupled to said timing control apparatus and responsive to saidquantized digital samples provided by said comparing means forpreventing application to said averagers of a predetermined fraction ofthose samples provided by said comparing means which indicate that thesecond signal is greater than or less than said ramp signal.

12. The analyzer defined in claim 1 further including a. means coupledwith said shift register for providing equal signal values theretowhereby said multiplying means output channels provide signal valuesproportional to said samples of the first input signal;

. fifth control means coupled to the scanning means to effectconnections of said averagers to said multiplying means output channelsin a complete sequence whereby the averagers in the first set areconnected sequentially, followed by those in the next set sequentially,and so on through all sets;

c. an auxiliary input for receiving a trigger signal;

d. means responsive to the auxiliary input and coupled to said fifthcontrol means for effecting one complete scanning sequence followingoccurrence of a trigger signal at said auxiliary input and preventinganother scan until occurrence of another trigger signal, and furtherincluding:

1. variable delay means for delaying the starting of said scanningsequence by a selectable interval following occurrence of a triggersignal, and

2. means for preventing said fifth control means from responding to atrigger signal occurring prior to completion ofa scanning sequence.

13. The analyzer defined in claim 1 wherein each of said averagerscomprises an input and an output; an averaging filter circuit consistingof a resistance coupled between the input and output, and an outputcapacitor coupled between the output and ground; and an input capacitorcoupled between the input and ground and having a capacitance value muchsmaller than the output capacitor.

14. The analyzer defined in claim 13 wherein said timing controlapparatus includes means for varying the rate of sampling of saidsignals and the rate of multiplying the samples thereof.

15. The analyzer defined in claim 13 wherein said timing controlapparatus includes means for varying the dwell time during which each ofsaid separate averagers is connected to said multiplying means outputchannels by said scanning means.

16. A system for analysis of first and second electrical signals,comprising:

a. A first sampling means for providing samples of the first signal,

b. a second sampling means for providing digital samples of the secondsignal, said second sampling means including a digital comparator forquantizing the second signal with respect to a reference level toprovide said digital samples, a reference signal generating means forgenerating a pseudorandom digital code having a uniform probabilitydistribution over the full scale range of the second signal to theapplied to said system, and means for connectin said re erence signalgenerating means to said digita comparator;

a multiplying means having one or more multiplication channels beingcoupled to said first and second sampling means for multiplying saiddigital samples by said samples from said first sampling means;

d. an averaging means including a plurality of signal averagerscoupledto each of said multiplication channels; and t e. a timing controlapparatus, including l. first control means coupled to the firstsampling means to effect sampling of the first signal;

2. second control means coupled to the second sampling means. saidsecond control means further including means stepping said referencesignal generating means from one value of said pseudorandom digital codeto the next in synchronism with the sampling of said second signal.

UNITED STATES PATENT OFFICE CERTEFECATE OF CORRECTIUN Patent No.3,626,168 Dated December 7, 1971 Inventor s Keith H. Norsworthy It iscertified that error appears in the above-identified patent and thatsaid Letters .Pat'nt are hereby corrected as shown below:

Column 15, line 6, after "by" said should be inserted.

Column 16;} line 19, delete I Signed and sealed this 10th day of October1972.

(SEAL) Attest: EDWARD M.FLETCI-ER,JR. ROBERT GOTTSCHALK AttestingOfficer Commissioner of Patents UNITED STATES PATENT OFFICE CERTEFICATEOF CGRRECTION Patent No. 3 ,626,l68 Dated December 7 1971 lnventofls)KeithH. Norsworthy It is certified that error appears in theabove-identified patent and that said Letters .Pat''iit are herebycorrected as shown below:

Column 15, line 6, after "by" said should be inserted.

' Column 16 line 19, delete 1 Signed and sealed this 10th day of October1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents

1. A system for analysis of first and second electrical signals,comprising: a. first sampling means for providing samples of the firstsignal; b. second sampling means for providing quantized digital samplesof the second signal; c. a shift register coupled to the second samplingmeans for receiving and storing successively derived values of saidquantized digital samples, said register having Q-stages into which saidsamples are shifted sequentially, where Q is an integer; d. multiplyingmeans having Q multiplication channels, each channel being coupled tothe first sampling means and to one of the shift register stages formultiplying said quantized digital samples stored therein by samplesfrom said first sampling means; e. averaging means including Q sets ofseparate signal averagers, each set being response to one of saidmultiplication channels, respectively, and each consisting of aplurality P of said averagers, where the product P(Q) equals the numberof desired output values; f. scanning means for intermittentlyconnecting each of said Q multiplication channels successively to eachof the P averagers in the set of averagers responsive thereto; and g.timing control apparatus including:
 1. first control means coupled tothe first sampling means to effect sampling of the first signal atintervals N Delta Tau , where N is an integer equal to unity, P1 or P1;2. second control means coupled to second sampling means to effectsampling of the second signal at intervals M Delta Tau , where M is aninteger equal to P;
 3. third control means coupled to the shift registerto effect shifting of second signal samples at intervals R Delta Tau ,where R is an integer equal to one of the integers N and M, and 4.fourth control means coupled to the scanning means for effectingconnections of each multiplication channel to the separate averagers inthe set responsive thereto, sequentially at intervals N Delta Tau . 2.second control means coupled to second sampling means to effect samplingof the second signal at intervals M Delta Tau , where M is an integerequal to P;
 2. means for preventing said fifth control means fromresponding to a trigger signal occurring prior to completion of ascanning sequence.
 2. further comprising third means altering saidsecond control means to effect sampling of the second signal atintervals (N-1) Delta Tau or (N+1) Delta Tau , whereby M N-1 or N+1; 2.The system defined in claim 1 wherein: a. said timing control apparatusincludes mode selection means establishing a first mode of operation,including:
 2. second means altering said third control means to effectshifting of said shift register at intervals M Delta Tau (R M); and b.each of said Q sets of averagers includes plurality M of said averagers(P M).
 2. second control means coupled to the second sampling means,said second control means further including means stepping saidreference signal generating means from one value of said pseudorandomdigital code to the next in synchronism with the sampling of said secondsignal.
 3. The system defined in claim 2 wherein: a. said mode selectionmeans establishes a second mode of operation in said system:
 3. saidsecond means alters said third control means to effect shifting of saidshift register at intervals N Delta Tau , whereby R N; and b. said thirdcontrol means further includes an auxiliary control for shifting saidregister one extra shift for each Nth shift thereof.
 3. third controlmeans coupled to the shift register to effect shifting of second signalsamples at intervals R Delta Tau , where R is an integer equal to one ofthe integers N and M, and
 4. fourth control means coupled to thescanning means for effecting connections of each multiplication channelto the separate averagers in the set responsive thereto, sequentially atintervals N Delta Tau .
 4. The system defined in claim 3 wherein saidtiming control apparatus includes: a. variable frequency clock means forproviding a basic timing waveform; b. said first control means and saidfourth control means include a ring counter having M+1 output stagessuccessively energized in response to said basic timing waveform; c.said first altering means of said mode selection means utilizes said Moutput stages thereof for said first mode of operation and utilizingsaid M+1 output stages for said second mode of operation; d. said firstcontrol means and said fourth control means each including means coupledto the first output stage of said ring counter.
 5. The system defined inclaim 4 wherein said timing control apparatus further includes: a. asecond ring counter within said second and third control means having Moutput stages successively energized in response to an applied timingwaveform; b. said third altering means of said mode selection meansfurther including a switch coupled to the first output stage of thefirst mentioned ring counter and to said clock means for selectivelyapplying to the input of said second counter the waveform provided atthe first output stage of said first mentioned ring counter for firstmode of operation and applying said basic timing waveform thereto forsaid second mode of operation; and c. said second and third controlmeans include means coupled to the waveform provided at the first outputstage of said second ring counter.
 6. The system defined in claim 1wherein said timing control apparatus includes: a. first means alteringsaid second control means to effect sampling of the second signal atintervals (N-1) Delta Tau or (N+1) Delta Tau , whereby M N-1 or N+1 andN>1; b. second means altering said third control means to effectshifting of said shift register at intervals N Delta Tau , whereby R+N;c. said third control means further includes an auxiliary control forshifting said register one extra shift for each Nth shift thereof; and,d. each of said Q sets of averagers includes a plurality N-1 or N+1 ofsaid averagers, whereby P N-1 or N+1.
 7. The analyzer defined in claim 1wherein said second sampling means includes: a. a digital comparator forproviding said quantized digital samples of the second signal withrespect to a reference signal, b. reference signal generating means forgenerating a psuedoransom digital code having a uniform probabilitydistribution over the full scale range of the second signal to beapplied to said analyzer, said generating means being responsive to saidsecond control means for stepping from one value of said code to thenext in synchronism with sampling of said second signal, and c. meansfor connecting said generating means to said comparator.
 8. The analyzerdefined in claim 1, including: a. a digital comparator for providingsaid quantized digital samples of said second signal with respect toreference level, b. a variable length shift register interposed betweensaid comparator and the first-mentioned shift register for providing aselectable amount of precomputation delay prior to multiplication ofsaid first and second signal samples, and c. means coupling saidvariable length shift register to said second control means foR shiftingsaid quantized digital samples of said second signal at intervals MDelta Tau .
 9. The analyzer defined in claim 1, further including: a.means for generating a ramp signal, b. means for comparing the secondsignal with said ramp signal and providing said quantized digitalsamples indicating whether the second signal is greater or less thansaid ramp signal, c. means for rendering said shift register ineffectiveand for applying signals corresponding to said quantized digital samplesto said multiplication means output channels, d. fifth control meanscoupled to the scanning means to effect intermittent connections of saidseparate averagers to said output channels in sequence whereby theaveragers in the first set are connected sequentially, followed by thosein the next set sequentially, through all sets, and e. sixth controlmeans coupled to said ramp signal generating means to effect onerepetition of said ramp signal in synchronism with each completesequence of connections by said scanning means.
 10. The analyzer definedin claim 9, further including: a. means for providing a constant-levelreference signal Delta V and adding it to said ramp signal to form a sumsignal; b. second comparing means for comparing said second signal tosaid sum signal and providing quantized signal values indicating whetherthe second signal is greater or less than said sum signal; c. an ORcircuit responsive to both of said comparing means for providing saidquantized digital samples indicating whether said second signal iswithin Delta V of said ramp signal; and d. means for preventingapplication of said quantized digital samples from the first comparingmeans to said multiplication means output channels and applying theretosaid quantized digital samples provided by said Or circuit.
 11. Theanalyzer defined in claim 9 further including weighting means coupled tosaid timing control apparatus and responsive to said quantized digitalsamples provided by said comparing means for preventing application tosaid averagers of a predetermined fraction of those samples provided bysaid comparing means which indicate that the second signal is greaterthan or less than said ramp signal.
 12. The analyzer defined in claim 1further including a. means coupled with said shift register forproviding equal signal values thereto whereby said multiplying meansoutput channels provide signal values proportional to said samples ofthe first input signal; b. fifth control means coupled to the scanningmeans to effect connections of said averagers to said multiplying meansoutput channels in a complete sequence whereby the averagers in thefirst set are connected sequentially, followed by those in the next setsequentially, and so on through all sets; c. an auxiliary input forreceiving a trigger signal; d. means responsive to the auxiliary inputand coupled to said fifth control means for effecting one completescanning sequence following occurrence of a trigger signal at saidauxiliary input and preventing another scan until occurrence of anothertrigger signal, and further including:
 13. The analyzer defined in claim1 wherein each of said averagers comprises an input and an output; anaveraging filter circuit consisting of a resistance coupled between theinput and output, and an output capacitor coupled between the output andground; and an input capacitor coupled between the input and ground andhaving a capacitance value much smaller than the output capacitor. 14.The analyzer defined in claim 13 wherein said timing control apparatusincludes means for varying the rate of sampling of said signaLs and therate of multiplying the samples thereof.
 15. The analyzer defined inclaim 13 wherein said timing control apparatus includes means forvarying the dwell time during which each of said separate averagers isconnected to said multiplying means output channels by said scanningmeans.
 16. A system for analysis of first and second electrical signals,comprising: a. A first sampling means for providing samples of the firstsignal, b. a second sampling means for providing digital samples of thesecond signal, said second sampling means including a digital comparatorfor quantizing the second signal with respect to a reference level toprovide said digital samples, a reference signal generating means forgenerating a pseudorandom digital code having a uniform probabilitydistribution over the full scale range of the second signal to theapplied to said system, and means for connecting said reference signalgenerating means to said digital comparator; c. a multiplying meanshaving one or more multiplication channels being coupled to said firstand second sampling means for multiplying said digital samples by saidsamples from said first sampling means; d. an averaging means includinga plurality of signal averagers coupled to each of said multiplicationchannels; and e. a timing control apparatus, including